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<title>PCMPEQQ — Compare Packed Qword Data for Equal </title></head>
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<h1>PCMPEQQ — Compare Packed Qword Data for Equal</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 38 29 /r PCMPEQQ <em>xmm1, xmm2/m128</em></td>
<td>RM</td>
<td>V/V</td>
<td>SSE4_1</td>
<td>Compare packed qwords in <em>xmm2/m128</em> and <em>xmm1</em> for equality.</td></tr>
<tr>
<td>VEX.NDS.128.66.0F38.WIG 29 /r VPCMPEQQ <em>xmm1, xmm2, xmm3/m128</em></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed quadwords in <em>xmm3/m128 </em>and <em>xmm2 </em>for equality.</td></tr>
<tr>
<td>VEX.NDS.256.66.0F38.WIG 29 /r VPCMPEQQ <em>ymm1, ymm2, ymm3 /m256</em></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed quadwords in <em>ymm3/m256 </em>and <em>ymm2</em> for equality.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W1 29 /r</p>
<p>VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Compare Equal between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W1 29 /r</p>
<p>VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Compare Equal between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W1 29 /r</p>
<p>VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Compare Equal between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the source operand (second operand).  If a pair of data elements is equal, the corresponding data element in the desti-nation is set to all 1s; otherwise, it is set to 0s.</p>
<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<p>EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
<h2>Operation</h2>
<p><strong>PCMPEQQ (with 128-bit operands)</strong></p>
<pre>IF (DEST[63:0] = SRC[63:0])
    THEN DEST[63:0] (cid:197) FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] (cid:197) 0; FI;
IF (DEST[127:64] = SRC[127:64])
    THEN DEST[127:64] (cid:197) FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] (cid:197) 0; FI;
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>COMPARE_QWORDS_EQUAL (SRC1, SRC2)</strong></p>
<pre>    IF SRC1[63:0] = SRC2[63:0]
    THEN DEST[63:0] (cid:197)FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] (cid:197)0; FI;
    IF SRC1[127:64] = SRC2[127:64]
    THEN DEST[127:64] (cid:197)FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] (cid:197)0; FI;</pre>
<p><strong>VPCMPEQQ (VEX.128 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_QWORDS_EQUAL(SRC1,SRC2)
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPCMPEQQ (VEX.256 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] (cid:197)COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPCMPEQQ (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k2[j] OR *no writemask*
         THEN
              IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP (cid:197) SRC1[i+63:i] = SRC2[63:0];
                    ELSE CMP (cid:197) SRC1[i+63:i] = SRC2[i+63:i];
              FI;
              IF CMP = TRUE
                    THEN DEST[j] (cid:197) 1;
                    ELSE DEST[j] (cid:197) 0; FI;
         ELSE
                    DEST[j] (cid:197) 0
                                                    ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);</p>
<p>VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);</p>
<p>VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);</p>
<p>VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);</p>
<p>VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);</p>
<p>VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);</p>
<p>(V)PCMPEQQ:</p>
<p>__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);</p>
<p>VPCMPEQQ:</p>
<p>__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded VPCMPEQQ, see Exceptions Type E4.</p></body></html>